Patterned wafer defect inspection of integrated circuit (IC) chips locates the failures in chip manufacturing process, and thus leads to yield improvement by fine tuning the process parameters to minimize failure rates. There are two major types of semiconductor wafer inspection techniques—light optical inspection, which uses a light source as an illumination source, and scanning electron beam inspection, which uses electrons as an illumination source.
Optical inspection systems often use parallel imaging techniques, which allows a high data acquisition rate and provides a high throughput of wafer inspected per hour. For a 300 mm wafer, it typically takes a few hours for an optical inspection system to scan the whole wafer. An optical inspection system's resolution is limited by diffraction aberration due to relatively large wavelengths of photons. Compared to photons, electrons have significantly smaller wavelength, which provides scanning electron beam inspection tools higher resolution and capability (relative to optical inspection systems) to identify wafer defects of a few nanometers in size. However, scanning electron beam inspection tools use a sequential data acquisition method, which limits the throughput of wafers inspected. For example, currently available systems can take more than a month to completely inspect a 300 mm wafer at the 20 nm IC design rule. Therefore, many researchers have proposed multiple electron beam system to scan and inspect the same wafer for parallel data acquisition in order to achieve the same high resolution with increased throughput.
A multiple electron beam inspection system utilizing parallel data acquisition may increase the throughput and shorten the time to inspect a wafer. However, the data acquisition rate of a scanning electron beam inspection system is limited to about 400 mega pixel per second. Therefore, more than 10,000 ideal parallel electron beams are needed to scan a full wafer within an hour for 14 nm and 10 nm chip design rules. It is expensive and unpractical to build a multi-column hardware with 10,000 ideal beams. On the other hand, it is relatively easy to make a multi-column system with about 100 beams, but such a multi-column system will take more than a week to scan a full wafer. Many defect inspection applications do not require defect information of a full wafer, and only a part of a wafer needs to be inspected for these applications. For example, defects on a photomask (reticle) will be printed at the same coordinate of different repeated patterned regions on a wafer. Therefore, these repeating defects from photomask can be capture by inspecting only one of the repeated patterned regions. For partial wafer inspection applications, it is very difficult to efficiently collect only desired information because the imaging positions are fixed by the multi-column hardware while the targeted inspection regions of the integrated circuit chips are distributed on a production wafer according to chip dimensions. All multi-column hardware, which target to only inspect part of the wafer, suffer from this misalignment between column arrangements and chip arrangements on a production wafer.